A Phase Locked Loop (PLL) circuit is typically used for frequency control. The PLL can be configured as, for example, a modulator, a demodulator, a frequency multiplier, a tracking generator, and as a clock recovery circuit. Each of these applications demands different characteristics, but they all use the same basic PLL circuit architecture.
Referring to FIG. 1, a PLL 1 is an electronic circuit with a voltage-driven or a current-driven oscillator that is constantly adjusted to match the phase of, and thus lock on to, the frequency of an input signal. In addition to stabilizing a particular communications channel (keeping it set to a particular frequency), a PLL can be used to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, or multiply or divide a frequency. PLLs are frequently used in wireless communication systems, particularly where signals are carried using frequency modulation (FM) or phase modulation (PM). PLLs can also be used in systems that employ amplitude modulation (AM). PLLs are more commonly used for digital data transmission, but can also be designed for use with analog information. Phase-locked loop devices are more commonly manufactured as integrated circuits (ICs), although discrete circuits are typically used for microwave applications.
A PLL includes a voltage-controlled oscillator (VCO) 2 that is typically tuned using a semiconductor diode known as a varactor. The VCO 2 is initially tuned to a frequency close to the desired receiving or transmitting frequency. A circuit referred to as a phase comparator or as a phase detector 3 causes the VCO 2 to seek and lock onto the desired frequency, based on the output of a crystal-controlled reference oscillator (frequency reference input) and the VCO frequency. This procedure relies on a feedback scheme, wherein a feedback control system controls the phase of the VCO. In a common approach the frequency reference signal is applied to one input of the phase detector 3, and the other input of the phase detector is connected to the output of a divide-by-N counter 4. Normally the frequencies of both input signals will be approximately equal, as the VCO 2 runs at N times the frequency of the reference frequency. The output of the phase detector 3 is a voltage proportional to the phase difference between the two inputs. This signal is applied to a loop filter 5. It is the loop filter 5 that determines the dynamic characteristics of the PLL, as the filtered signal controls the VCO 2 (which operates at a frequency that is N times the input frequency reference). If the frequency of the VCO 2 departs from the selected crystal reference frequency, the phase comparator 3 produces an error voltage that is applied to the varactor of the VCO 2, bringing the VCO 2 back to the reference frequency. The PLL, VCO, reference oscillator, and phase comparator together comprise a frequency synthesizer, and wireless equipment that uses this type of frequency control is said to be “frequency-synthesized”.
Since a PLL requires a certain amount of time to lock on the frequency of an incoming signal, the intelligence on the signal (voice, video, or data) can be obtained directly from the waveform of the measured error voltage, which should reflect exactly the modulated information on the signal.
In the PLL-based frequency synthesizer, the VCO 2 produces the output carrier signal at the desired frequency based on the VCO frequency control (Vctr1) signal. In the PLL configuration, this control is achieved by the feedback loop, with the VCO output signal coupled via the feedback loop to the phase detector 3 that compares the VCO signal phase and frequency to that of the fixed-frequency reference (Fin) signal, and produces the frequency control (Vctr1) signal corresponding to the phase difference between the VCO signal and the fixed-accurate frequency signal. This frequency control signal (Vctr1) is filtered by the low pass loop filter 5 and is then applied to the VCO 2. The result is that in the steady state the VCO output signal frequency matches that of the fixed-frequency reference signal (is actually N times Fin for the embodiment shown in FIG. 1).
As was explained above, to set the VCO output frequency the frequency divider 4 is included in the PLL feedback loop between the VCO output and the phase detector to enable division of the frequency of the VCO output signal to a frequency that is a multiple of that of the fixed-frequency reference source (Fin).
In a mobile station, such as a cellular telephone, the VCO output frequency can be used to generate the transmitted signal. A modulated transmitted carrier signal can be generated, for example, by mixing a signal from a separate modulator with the VCO output signal, where the mixing result includes the desired modulation. Alternatively, the VCO 2 itself can be modulated.
In direct open-loop modulation, modulating data is directly applied to the VCO 2, or to an appropriate node in the PLL 1 that enables access to the VCO 2. In direct open-loop PLL modulation the feedback loop is periodically closed and the PLL 1 adjusts the carrier frequency, during times that modulation is not performed. However, the required opening of the PLL feedback loop during modulation limits this technique to only burst mode modulation, as the PLL feedback loop must be periodically closed to enable carrier frequency adjustment.
One technique to overcome the foregoing limitation in burst mode open-loop modulation is to use closed-loop modulation, where the data stream is directly applied to the VCO 2, or to a node in the PLL 1 enabling access to the VCO 2, but without opening the PLL feedback loop. In this case there may be several nodes the where data stream can be applied. These are typically referred to as two point modulation and three point modulation, according to the number of modulating nodes in the PLL system.
However, disadvantages of the closed-loop modulation technique arise when the modulating signal bandwidth is larger than the loop bandwidth of the frequency synthesizer.
There are known techniques to avoid this problem. For example, U.S. Pat. No.: 4,242,649, “Method and Apparatus for Modulating a Phased Locked Loop”, Washburn et al., discloses a method where the modulation signal is processed to compensate for the transfer functions of loop components, and the processed signal is summed with the loop signal at a point between the output terminals of the phase detector and the low-pass filter of the loop. The processing of the modulation signal involves a pre-emphasis of the signal to compensate for the transfer functions of the loop circuitry located between the voltage controlled oscillator and the summing junction.
It is also well known to digitally process modulating signals to adjust the modulating signal bandwidth prior to feeding the modulating signal to PLL synthesizer. For example, EP 040823 8 A2, “A Frequency Synthesiser”, Johnson, discloses a method for producing continuous phase modulation of a carrier frequency by application of digital modulating signals. Modulating signals are digitally processed, pre-shaped and fed to a variable frequency divider and to a loop node located between the phase detector and the VCO.
Compensating the transfer functions of PLL loop components is known by pre-emphasizing the modulating signal. However, further problems can arise during an integrated circuit (IC) manufacturing process. Due to the analog nature of the PLL loop filter 5, the typical IC component tolerance variations, as well as temperature-related effects, can be very detrimental to assuring uniform operation over a number of devices. Also, in mobile phone applications the analog loop filter approach is relied upon.
One method to solve process variation and temperature variation problems is disclosed in the publication: D. R. McMahill, C. G. Sodini, “A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated sigma-delta frequency synthesizer”, IEEE Journal of Solid-State Circuits, pps. 18–26, January 2002. The basic idea behind the approach of McMahill et al. is that an automatic calibration circuit uses the transmit data to determine an ideal RF output phase trajectory. The actual output phase trajectory is monitored and the PLL is tuned to produce the desired response. By tuning the PLL response to match the inverse of the pre-compensation filter, an efficient fixed coefficient digital filter for a Gaussian filter is provided, and pre-compensation may be used. The loop filter transfer function is adjusted according to component variations.
Also of general interest to the teachings of this invention is U.S. Pat. No.: 6,064,272, “Phase Interpolated Fractional-N Frequency Synthesizer with On-Chip Tuning”, W. Rhee, as well as the following commonly assigned U.S. Pat. No.: 5,079,520, “Interpolating Phase-Locked Loop Frequency Synthesizer”, J. Rapeli; U.S. Pat. No. 5,751,194, “Phase-Locked Loop Having Charge Pump Controlled According to Temperature and Frequency”, M. Haapanen et al.; U.S. Pat. No. 5,920,556, “Frequency Modulation Using a Phase-Locked Loop”, K. Jorgensen; and U.S. Pat. No. 5,983,081, “Method for Generating Frequencies in a Direct Conversion Transceiver of a Dual Band Radio Communication System, A Direct Conversion Transceiver of a Dual Band Radio Communication System and the Use of This Method and Apparatus in a Mobile Station”, K. Lehtinen. Reference may also be had to commonly assigned U.S. Patent Application Publication No.: US 2001/0045864 A1, Nov. 29, 2001, “Method and Arrangement for Calibrating an Active Filter”, Kimppa et al.
The foregoing problems exist as well in a polar transmitter, wherein the signal is divided into phase and amplitude components, as opposed to the traditional division of the signal into in-phase and quadrature (I and Q) components.
What would be desirable to provide is a new and improved compensation technique that is better suited for mobile station applications than the prior art component value and temperature variation compensation techniques. Prior to this invention this need was not adequately addressed.